A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

This paper presents a heuristic technique for automatically generating different architectures for an analog system. The architecture generator (AG) starts from a signal-flow graph (SFG) specification of a system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in an SFG. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.